LPM_FF

4.4.2 LPM_FF

Flip-flop: D type or Toggle

Ports

Port Name	Type	Usage	Description	Comments
Data	I	Required	TFF: Toggle enable DFF: Data input Data input during Aload or Sload	Vector, LPM_Width wide
Clock	I	Required	Positive Edge Triggered
Enable	I	Optional	Enable all synchronous activities	Default is enabled (1)
Q	O	Required	Output of Flip-flops	Vector, LPM_Width wide
Sload	I	Note 1	TFF only: Load the Flip-flops with Data on the next clock.	Note 2, Note 4
Sset	I	Optional	Set Flip-flops to all 1's or to the value of LPM_Svalue, if present	Note 3, Note 4
Sclr	I	Optional	Clear the Flip-flops (set to all 0's)	Note 4
Aload	I	Note 1	TFF only: Load the Flip-flops with Data.	Note 4
Aset	I	Optional	Set Flip-flops to all 1's or to the value of LPM_Avalue, if present.	Note 3, Note 4
Aclr	I	Optional	Clear the Flip-flops (set to all 0's)	Note 4
TestEnab	I	Note 5	Test clock enable input
TestIn	I	Note 5	Serial test data input
TestOut	O	Note 5	Serial test data output	TestOut = Q_{LPM_Width-1}

Note 1: Aload and Sload are only applicable when LPM _FFType is TFF. If the LPM_FFType is DFF and these ports are connected, it is an ERROR.

Note 2: Synchronous load of LPM_TFF. For load operation Sload must be high (1) and Enable (the clock enable) must be High or unconnected.

Note 3: Sset and Aset will set the Flip-flops to the value of LPM_Svalue or LPM_Avalue repectively, if those values are present. If no LPM_Svalue is specified, then Sset will set the Flip-flops to all ones, likewise Aset.

Note 4: For outputs such as Q_ion the LPM_FF, Aload, Aset, Aclr, Sload, Sset and Sclr affect the output before polarity is applied.

Note 5: Either all of the Test ports must be connected or none of them.

Properties

Property	Usage	Value	Comments
LPM_Width	Required	LPM Value > 0	Width of input and output vectors
LPM_Avalue	Optional	LPM Value	Value loaded by Aset
LPM_Svalue	Optional	LPM Value	Value loaded by Sset
LPM_Pvalue	Optional	LPM Value	Value loaded at power-on
LPM_FFType	Optional	DFF \| TFF	Default is DFF

Functions

Aclr Aset Aload	Sclr Sset Sload	Clock	Enable	Test-Enab	Output
H	X	X	X	X	Asynchronous value. Note 1
L	H	rising edge	H	L	Synchronous value Note 2
L	H	rising edge	L	L	No change
L	L	rising edge	L	L	No change (clock not enabled)
L	L	rising edge	H	L	TFF: FF_i is toggled if Data_i is high (1). DFF: Data is loaded into the register
L	X	rising edge	X	H	Q_i is shifted into Q_i+1 TestIn is loaded into Q₀

The asynchronous value is determined by which asynchronous port is high: Aclr, Aset or Aload. If Aclr and Aset are both high, then the output is UNDEFINED. Aclr or Aset takes priority over Aload. Asynchronous controls have priority over synchronous controls. If the LPM_Avalue property is defined, then the Aset port, when active, will set the FFs to the value of the LPM_Avalue. Aload is not permitted when the LPM_FFType is DFF.
The synchronous value is determined by which synchronous port is high: Sclr, Sset or Sload. If more then one synchronous port is high, then Sclr takes priority over Sset which takes priority over Sload. Asynchronous controls have priority over synchronous controls. If the LPM_Svalue property is defined, then the Sset port, when active, will set the FFs to the value of the LPM_Svalue. Sload is not permitted when the LPM_FFType is DFF.