This code is for a 4-1 inverting multiplexor which takes in four 1-bit buses and which therefore requires two contol signals by which to select one of the inputs.
// behavioural-level description of an inverting multiplexor
module mux_beh (out, cnt1, cnt2, a, b, c, d);
output out;
input cnt1, cnt2, a, b, c, d;
reg out;
always @(cnt1 or cnt2 or a or b or c or d)
if (cnt1 == 1)
if (cnt2 == 1) out = ~a;
else out = ~b;
else if (cnt2 == 1) out = ~c;
else out = ~d;
endmodule // mux_gate
// behavioural-level description of an inverting multiplexor
module mux_beh_2 (out, cnt1, cnt2, a, b, c, d);
output out;
input cnt1, cnt2, a, b, c, d;
wire out1, out2;
assign out1 = (cnt1 == 1) ? ~a: ~b;
assign out2 = (cnt1 == 1) ? ~c: ~d;
assign out = (cnt2 == 1) ? out1: out2;
endmodule // mux_gate
// functional-level description of an inverting multiplexor
module mux_func (out, cnt1, cnt2, a, b, c, d);
output out;
input cnt1, cnt2, a, b, c, d;
assign out = ~((cnt1 & cnt2 & a) |
(~cnt1 & cnt2 & b) |
(cnt1 & ~cnt2 & c) |
(~cnt1 & ~cnt2 & d));
endmodule // mux_gate
// gate-level description of an inverting multiplexor
// USING HIERARCHY - first the original descirption of a 2-1
module mux_2_1 (out, cnt, a, b);
output out;
input cnt, a, b;
wire cntBar;
wire aval, bval;
not (cntBar, cnt);
and (aval, cnt, a);
and (bval, cntBar, b);
nor (out, aval, bval);
endmodule // mux_gate
module mux_gate (out, cnt1, cnt2, a, b, c, d);
output out;
input cnt1, cnt2, a, b, c, d;
wire out1, out2, outBar;
mux_2_1 name1 (out1, cnt1, a, b);
mux_2_1 name2 (out2, cnt1, c, d);
mux_2_1 freda (outBar, cnt2, out1, out2);
not (out, outBar);
endmodule // mux_gate
// NECESSARY TEST stimulus to verify designs
module stimulus;
reg a, b, c, d, cnt1, cnt2;
wire out1, out2, out3, out4;
integer i;
mux_beh_2 mod1 (out1, cnt1, cnt2, a, b, c, d);
mux_beh mod2 (out2, cnt1, cnt2, a, b, c, d);
mux_func mod3 (out3, cnt1, cnt2, a, b, c, d);
mux_gate mod4 (out4, cnt1, cnt2, a, b, c, d);
initial begin
for (i = 0; i <64; i = i + 1) begin
{a, b, c, d, cnt1, cnt2} = i[5:0];
#10 $display ($time, " %b %b %b %b %b %b - %b %b %b %b",
a, b, c, d, cnt1, cnt2, out1, out2, out3, out4);
end
#10 $finish;
end // initial begin
endmodule // stimulus
And the following code refers to a multiplexor which selects between two, four-bit inputs
// behavioural-level description of an inverting multiplexor
module mux_beh (out, cnt, a, b);
output [3:0] out;
input cnt;
input [3:0] a, b;
reg [3:0] out;
always @(cnt or a or b)
if (cnt == 1) out = ~a;
else out = ~b;
endmodule // mux_gate
// behavioural-level description of an inverting multiplexor
module mux_beh_2 (out, cnt, a, b);
output [3:0] out;
input cnt;
input [3:0] a, b;
assign out = (cnt == 1) ? ~a: ~b;
endmodule // mux_gate
// functional-level description of an inverting multiplexor
module mux_func (out, cnt, a, b);
output [3:0] out;
input cnt;
input [3:0] a, b;
assign out = ~(({4{cnt}} & a) | (~{4{cnt}} & b));
endmodule
/* sub-module for a hierarchical gate-level description */
module mux_bit(out, cnt, cntBar, a, b);
output out;
input cnt, cntBar, a, b;
wire aval, bval;
and (aval, cnt, a);
and (bval, cntBar, b);
nor (out, bval, aval);
endmodule
module mux_gate_2 (out, cnt, a, b);
output [3:0] out;
input cnt;
input [3:0] a, b;
wire cntBar;
not (cntBar, cnt);
mux_bit m0 (out[0], cnt, cntBar, a[0], b[0]);
mux_bit m1 (out[1], cnt, cntBar, a[1], b[1]);
mux_bit m2 (out[2], cnt, cntBar, a[2], b[2]);
mux_bit m3 (out[3], cnt, cntBar, a[3], b[3]);
endmodule
// gate-level description of an inverting multiplexor
module mux_gate (out, cnt, a, b);
output [3:0] out;
input cnt;
input [3:0] a, b;
wire cntBar;
wire [3:0] aval, bval;
not (cntBar, cnt);
and (aval[0], cnt, a[0]);
and (aval[1], cnt, a[1]);
and (aval[2], cnt, a[2]);
and (aval[3], cnt, a[3]);
and (bval[0], cntBar, b[0]);
and (bval[1], cntBar, b[1]);
and (bval[2], cntBar, b[2]);
and (bval[3], cntBar, b[3]);
nor (out[0], aval[0], bval[0]);
nor (out[1], aval[1], bval[1]);
nor (out[2], aval[2], bval[2]);
nor (out[3], aval[3], bval[3]);
endmodule // mux_gate
// NECESSARY TEST stimulus to verify designs
module stimulus;
reg [3:0] a, b;
reg c;
wire [3:0] out1, out2, out3, out4, out5;
integer i;
mux_beh_2 mod1 (out1, c, a, b);
mux_beh mod2 (out2, c, a, b);
mux_func mod3 (out3, c, a, b);
mux_gate mod4 (out4, c, a, b);
mux_gate_2 mod5 (out5, c, a, b);
initial begin
for (i = 0; i < 32; i = i + 1) begin
{b, c} = i[4:0];
a = ~b;
#10 $display ($time, " %b %b %b - %b %b %b %b %b",
a, b, c, out1, out2, out3, out4, out5);
end
#10 $finish;
end // initial begin
endmodule // stimulus