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'Structured' ASICs
arrive
By Ron
Wilson, EE Times
May 5, 2003 (10:23 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030505S0028

A whole new segment of
the ASIC business burst upon the market in the last year with a series of
announcements from chip vendors and their tool suppliers. The so-called
"structured ASICs" promise resource-starved design teams almost all the density,
performance and power efficiency of cell-based ASICs, but with significantly
shorter turnaround time and drastically lower nonrecurring expense-below $50,000
in some cases. Needless to say, the devices have created a stir.

So far, there have been four solid entries in the segment, plus two important
product lines that should be considered structured ASICs even though they differ
from the rest. The four clear candidates are from AMI Semiconductor (Pocatello,
Idaho), Chip Express (Santa Clara, Calif.), Lightspeed Semiconductor (Sunnyvale,
Calif.) and NEC Electronics (Santa Clara). The two closely related offerings are
the HardCopy product line from FPGA giant Altera Corp. (San Jose, Calif.) and
the RapidChip line from LSI Logic Corp. (Milpitas, Calif.).

Structured ASICs are based on a predefined logic fabric-in essence, an array
of prebuilt logic cells and an arrangement of configurable memory blocks. This
array can be fabricated up through the first few metal layers as if it were a
standard product, almost as a cross between an FPGA and a gate array. Then the
base wafers can be warehoused, waiting for an order.

A customer design, meanwhile, is accepted at the register-transfer or netlist
level and mapped onto the logic cells and memory blocks. The wafers are pulled
from inventory, the upper metal layers completed to implement the customer's
design and the finished wafers treated from there on out as if they were any
other sort of ASIC.

Since the hard parts-the critical mask layers, the majority of processing
steps and most of the expensive masks-are shared among all the users of the
technology, NRE can be quite small, as can turnaround time. And if the
architectural design is clever, the devices give up very little compared with a
full-up cell-based design. Of course, the real story always lurks behind the
word "if."
A matter of flavor
Not surprisingly, each of the
structured-ASIC product lines announced to date has a flavor of its own,
reflective of the vendor that produced it. The families from AMI and Lightspeed
reflect, to a greater or lesser degree, those companies' experiences in the
FPGA-conversion market. The Chip Express and NEC offerings are distinctly more
ASIC-flavored. Altera's HardCopy is explicitly promoted as an FPGA without the
programmable interconnect. LSI Logic's RapidChip is more accurately described as
a customizable application-specific standard product. Despite the strong
conceptual similarities, each of these lines has architectural details,
implementation choices and tool affinities that reflect its heritage. And these
differences can be important in finding the best family for a particular
application.

Some of the differences are obvious. For example, Altera's HardCopy devices
are nothing more nor less than Altera FPGAs with the programmable interconnect
replaced by hard interconnect lines. The underlying logic cell and memory
structure matches that of the equivalent FPGA. The intended design flow for the
devices is to develop the application using the FPGA flow, then simply move it
across.

LSI's RapidChip presents a different scenario. Devices in the family are
essentially application-specific platforms composed of all the major
intellectual-property (IP) blocks LSI deems necessary for a particular
application. The first announced member of the family, for example, has 48
high-speed I/O ports, six phase-locked loops, a double-data-rate DRAM port and a
number of SRAM ports as diffused IP blocks. In the die area not used by these
blocks, LSI provides approximately 3 million usable gates of uncommitted logic.
These are used to adapt the big IP blocks to a particular customer's needs.

The other four families fit better into the generalization of a cross between
an FPGA and a gate array. Except for a few serdes blocks or high-speed I/O pads
that are showing up in some lines (notably NEC's), the chips consist of
uncommitted logic cells and memory blocks-lightly structured blank slates on
which the users may write as they will. Yet even in these devices the structure
is significant.
Under the hood
Looking beneath the surface of all
the devices, differences start to appear. Perhaps the most obvious is in the
logic cells of which the devices are composed. And it is the logic cell that
separates most of the families from their nearest ancestors, gate arrays. In all
cases except one, the logic cells are a good deal larger than the transistor
pairs or quads that were used in sea-of-gates gate arrays.

The devices with the most complex logic cells are, no surprise, those with a
heritage of FPGA conversion. AMI's logic cell, for example, comprises "some RAM
and some simple logic functions," said AMI vice president Vince Hopkin. The
company, like most of its competitors, doesn't care to discuss the details of
its logic fabric without a nondisclosure agreement. But Hopkin added that the
cell was sufficiently complex to implement at least a simple flip-flop in a
single cell.

Lightspeed's basic logic block is apparently even more complex, including
multiplexers, a logic gate, a fully scannable flip-flop and buffers. As in FPGA
architectures, part of the power and the challenge of the architecture lies in
the ability to share resources in a single logic block among different nets.

At the other extreme, the Chip Express logic cell comprises only three muxes
and three inverters. Two cells are required to implement a simple D-type
flip-flop. And LSI's logic element is even smaller, based on an underlying
metal-programmable logic cell technology from Virage Logic (Fremont, Calif.).
Virage's metal-programmed technology may also underlie the NEC logic
element.

The devices also differ considerably in their approach to power and clock
distribution. The Lightspeed devices distribute power with a top metal layer,
dropping it down to dedicated power-routing segments in the first four,
non-user-configured metal layers. Similarly, Lightspeed constructs clock trees
after layout, using both the wires in user-dependent metal layers 5 and 6 and
dedicated, carefully spaced clock segments in layers 3 and 4. Chip Express, in
keeping with its gate arraylike flow, builds delay-locked loops and clock trees
from logic elements and user-determined metal. Power routing is fixed in metal
1. NEC does the bulk of its balanced clock tree routing in metal 1-3, but leaves
enough flexibility to permit multiple clock regions and gated clocks. Power is
delivered through a fixed grid transparent to the customer. AMI also delivers
power in a fixed grid in the lower layers, but synthesizes its clocks in upper
metal layers.

LSI Logic, with its large, fixed IP blocks, uses a common power grid across
its entire planned family of devices. Clocks are synthesized through a
proprietary system called the Clock Factory, with access to most of the metal
layers. Unlike the other vendors, LSI banks wafers at metal-1, so most layers
can respond to the needs of the customer design.

Test strategies also vary somewhat. Lightspeed is unusual in this regard,
offering full visibility and controllability of all the flip-flops on the chip
and also, uniquely, of many of the purely combinatorial cells. The result is
what Lightspeed terms unprecedented access for test and diagnosis. This access
also makes it possible to capture user clocks, apply them at speed and extract
signatures from the output of a block for delay-fault testing.

NEC provides scan chains that include all the flip-flops on the chip, as well
as boundary scan for the I/O pads. Senior product-design engineer Gary Smith
described the resulting methodology as "a cross between mux scan and LSSD
[level-sensitive scan design]." AMI similarly embeds scan cells in its array and
organizes the scan chains in accord with the customer's design. Chip Express
inserts scannable flip-flops into the user design before layout, then reorders
the scan chains after layout. LSI follows a similar methodology for the
user-defined portion of its chips, blending the resulting chains with the scan
chains provided in the company's diffused IP. All the vendors supply some form
of memory built-in self-test, and all provide loopbacks or other self-test
mechanisms for high-speed I/O.

At this stage, it is fair to say that the structured-ASIC lineup includes
distinct variations on a common theme. Choosing the right one will depend on the
application, the degree of vendor involvement the customer wishes and
predispositions about design flows. But the choices are there.

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