proc start_step { step } {
  set stopFile ".stop.rst"
  if {[file isfile .stop.rst]} {
    puts ""
    puts "*** Halting run - EA reset detected ***"
    puts ""
    puts ""
    return -code error
  }
  set beginFile ".$step.begin.rst"
  set platform "$::tcl_platform(platform)"
  set user "$::tcl_platform(user)"
  set pid [pid]
  set host ""
  if { [string equal $platform unix] } {
    if { [info exist ::env(HOSTNAME)] } {
      set host $::env(HOSTNAME)
    }
  } else {
    if { [info exist ::env(COMPUTERNAME)] } {
      set host $::env(COMPUTERNAME)
    }
  }
  set ch [open $beginFile w]
  puts $ch "<?xml version=\"1.0\"?>"
  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
  puts $ch "    </Process>"
  puts $ch "</ProcessHandle>"
  close $ch
}

proc end_step { step } {
  set endFile ".$step.end.rst"
  set ch [open $endFile w]
  close $ch
}

proc step_failed { step } {
  set endFile ".$step.error.rst"
  set ch [open $endFile w]
  close $ch
}

set_msg_config -id {HDL 9-1061} -limit 100000
set_msg_config -id {HDL 9-1654} -limit 100000

start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
  create_msg_db init_design.pb
  set_param xicom.use_bs_reader 1
  create_project -in_memory -part xc7z020clg484-1
  set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
  set_property design_mode GateLvl [current_fileset]
  set_param project.singleFileAddWarning.threshold 0
  set_property webtalk.parent_dir D:/Work/2016_17_CENG3430/TestVGA/TestVGA/TestVGA.cache/wt [current_project]
  set_property parent.project_path D:/Work/2016_17_CENG3430/TestVGA/TestVGA/TestVGA.xpr [current_project]
  set_property ip_output_repo D:/Work/2016_17_CENG3430/TestVGA/TestVGA/TestVGA.cache/ip [current_project]
  set_property ip_cache_permissions {read write} [current_project]
  add_files -quiet D:/Work/2016_17_CENG3430/TestVGA/TestVGA/TestVGA.runs/synth_1/TestVGA.dcp
  read_xdc D:/Work/2016_17_CENG3430/TestVGA/TestVGA.xdc
  link_design -top TestVGA -part xc7z020clg484-1
  write_hwdef -file TestVGA.hwdef
  close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
  step_failed init_design
  return -code error $RESULT
} else {
  end_step init_design
  unset ACTIVE_STEP 
}

start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
  create_msg_db opt_design.pb
  opt_design 
  write_checkpoint -force TestVGA_opt.dcp
  report_drc -file TestVGA_drc_opted.rpt
  close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
  step_failed opt_design
  return -code error $RESULT
} else {
  end_step opt_design
  unset ACTIVE_STEP 
}

start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
  create_msg_db place_design.pb
  implement_debug_core 
  place_design 
  write_checkpoint -force TestVGA_placed.dcp
  report_io -file TestVGA_io_placed.rpt
  report_utilization -file TestVGA_utilization_placed.rpt -pb TestVGA_utilization_placed.pb
  report_control_sets -verbose -file TestVGA_control_sets_placed.rpt
  close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
  step_failed place_design
  return -code error $RESULT
} else {
  end_step place_design
  unset ACTIVE_STEP 
}

start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
  create_msg_db route_design.pb
  route_design 
  write_checkpoint -force TestVGA_routed.dcp
  report_drc -file TestVGA_drc_routed.rpt -pb TestVGA_drc_routed.pb -rpx TestVGA_drc_routed.rpx
  report_methodology -file TestVGA_methodology_drc_routed.rpt -rpx TestVGA_methodology_drc_routed.rpx
  report_timing_summary -warn_on_violation -max_paths 10 -file TestVGA_timing_summary_routed.rpt -rpx TestVGA_timing_summary_routed.rpx
  report_power -file TestVGA_power_routed.rpt -pb TestVGA_power_summary_routed.pb -rpx TestVGA_power_routed.rpx
  report_route_status -file TestVGA_route_status.rpt -pb TestVGA_route_status.pb
  report_clock_utilization -file TestVGA_clock_utilization_routed.rpt
  close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
  write_checkpoint -force TestVGA_routed_error.dcp
  step_failed route_design
  return -code error $RESULT
} else {
  end_step route_design
  unset ACTIVE_STEP 
}

start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
  create_msg_db write_bitstream.pb
  catch { write_mem_info -force TestVGA.mmi }
  write_bitstream -force -no_partial_bitfile TestVGA.bit 
  catch { write_sysdef -hwdef TestVGA.hwdef -bitfile TestVGA.bit -meminfo TestVGA.mmi -file TestVGA.sysdef }
  catch {write_debug_probes -quiet -force debug_nets}
  close_msg_db -file write_bitstream.pb
} RESULT]
if {$rc} {
  step_failed write_bitstream
  return -code error $RESULT
} else {
  end_step write_bitstream
  unset ACTIVE_STEP 
}

