# 
# Synthesis run script generated by Vivado
# 

set_param xicom.use_bs_reader 1
set_msg_config -id {HDL 9-1061} -limit 100000
set_msg_config -id {HDL 9-1654} -limit 100000
create_project -in_memory -part xc7z020clg484-1

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir D:/Work/2016_17_CENG3430/TestVGA/TestVGA/TestVGA.cache/wt [current_project]
set_property parent.project_path D:/Work/2016_17_CENG3430/TestVGA/TestVGA/TestVGA.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
set_property ip_output_repo d:/Work/2016_17_CENG3430/TestVGA/TestVGA/TestVGA.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_vhdl -library xil_defaultlib D:/Work/2016_17_CENG3430/TestVGA/TestVGA/TestVGA.srcs/sources_1/new/TestVGA.vhd
foreach dcp [get_files -quiet -all *.dcp] {
  set_property used_in_implementation false $dcp
}
read_xdc D:/Work/2016_17_CENG3430/TestVGA/TestVGA.xdc
set_property used_in_implementation false [get_files D:/Work/2016_17_CENG3430/TestVGA/TestVGA.xdc]


synth_design -top TestVGA -part xc7z020clg484-1


write_checkpoint -force -noxdef TestVGA.dcp

catch { report_utilization -file TestVGA_utilization_synth.rpt -pb TestVGA_utilization_synth.pb }
