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-- Company: 
-- Engineer: 
-- 
-- Create Date: 03/16/2017 02:29:48 PM
-- Design Name: 
-- Module Name: TestVGA - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TestVGA is
    Port ( clk : in STD_LOGIC;
           VS : out STD_LOGIC;
           HS : out STD_LOGIC;
           R1 : out STD_LOGIC;
           R2 : out STD_LOGIC;
           R3 : out STD_LOGIC;
           R4 : out STD_LOGIC;
           G1 : out STD_LOGIC;
           G2 : out STD_LOGIC;
           G3 : out STD_LOGIC;
           G4 : out STD_LOGIC;
           B1 : out STD_LOGIC;
           B2 : out STD_LOGIC;
           B3 : out STD_LOGIC;
           B4 : out STD_LOGIC);
end TestVGA;

architecture Behavioral of TestVGA is
constant Hoffset : integer := 70;
signal counterX: integer;
signal counterY: integer;
signal hsw: integer;
signal PCLK_count: integer;
signal pixelclk: STD_LOGIC:='0';
signal tmp_hs: STD_LOGIC:='0';
signal tmp_vs: STD_LOGIC:='0';

begin
  process(clk)
  begin
    if rising_edge(clk) then
      if (PCLK_count=1) then
        pixelclk <= not pixelclk; -- 40nS pixel clock (100MHz/4)
        PCLK_count <= 0;
      else
        PCLK_count <= PCLK_count + 1;
      end if;
    end if;
  
    if rising_edge(pixelclk) then
      if (counterX=799) then
        tmp_hs <= '1';
        counterX <= 0;
      else
        counterX <= counterX + 1;   
      end if;
      
    if (tmp_hs='1') then
      if (pixelclk='1') then
        if (hsw=25) then  -- pulse width of HS ~ 1us
          tmp_hs <= '0';
          hsw <= 0;
        else
          hsw <= hsw + 1;
        end if;
      end if;
    end if;
    
    HS <= tmp_hs;   -- HS 31.25KHz
    end if;
    
    if rising_edge(tmp_hs) then
      if (counterY=519) then
        tmp_vs <= '1';
        counterY <= 0;
      else
        counterY <= counterY + 1;   
      end if;
          
      if (tmp_vs='1') then
        if (pixelclk='1') then
           tmp_vs <= '0';
        end if;
      end if;
      
      VS <= tmp_vs;   -- VS 60Hz
    end if;
 
 -- Test pattern    
    if (counterX<Hoffset) then
      R1 <= '0';
      R2 <= '0';
      R3 <= '0';
      R4 <= '0';
      G1 <= '0';
      G2 <= '0';
      G3 <= '0';
      G4 <= '0';
      B1 <= '0';
      B2 <= '0';
      B3 <= '0';
      B4 <= '0';
    end if;
       
    if (counterX>=Hoffset) and (counterX<(80+Hoffset)) then
      R1 <= '1';
      R2 <= '1';
      R3 <= '1';
      R4 <= '1';
      G1 <= '0';
      G2 <= '0';
      G3 <= '0';
      G4 <= '0';
      B1 <= '0';
      B2 <= '0';
      B3 <= '0';
      B4 <= '0';
    end if;  
    
    if (counterX>=(80+Hoffset)) and (counterX<(80*2+Hoffset)) then
      R1 <= '0';
      R2 <= '0';
      R3 <= '0';
      R4 <= '0';
      G1 <= '1';
      G2 <= '1';
      G3 <= '1';
      G4 <= '1';
      B1 <= '0';
      B2 <= '0';
      B3 <= '0';
      B4 <= '0';
    end if;  
    
    if (counterX>=(80*2+Hoffset)) and (counterX<(80*3+Hoffset)) then
      R1 <= '0';
      R2 <= '0';
      R3 <= '0';
      R4 <= '0';
      G1 <= '1';
      G2 <= '1';
      G3 <= '1';
      G4 <= '1';
      B1 <= '1';
      B2 <= '1';
      B3 <= '1';
      B4 <= '1';
    end if;

    if (counterX>=(80*3+Hoffset)) and (counterX<(80*4+Hoffset)) then
      R1 <= '0';
      R2 <= '0';
      R3 <= '0';
      R4 <= '0';
      G1 <= '0';
      G2 <= '0';
      G3 <= '0';
      G4 <= '0';
      B1 <= '1';
      B2 <= '1';
      B3 <= '1';
      B4 <= '1';
    end if;    

    if (counterX>=(80*4+Hoffset)) and (counterX<(80*5+Hoffset)) then
      R1 <= '1';
      R2 <= '1';
      R3 <= '1';
      R4 <= '1';
      G1 <= '0';
      G2 <= '0';
      G3 <= '0';
      G4 <= '0';
      B1 <= '1';
      B2 <= '1';
      B3 <= '1';
      B4 <= '1';
    end if;  
    
   if (counterX>=(80*5+Hoffset)) and (counterX<(80*6+Hoffset)) then
      R1 <= '1';
      R2 <= '1';
      R3 <= '1';
      R4 <= '1';
      G1 <= '1';
      G2 <= '1';
      G3 <= '1';
      G4 <= '1';
      B1 <= '0';
      B2 <= '0';
      B3 <= '0';
      B4 <= '0';
    end if;      

    if (counterX>=(80*6+Hoffset)) and (counterX<(80*7+Hoffset)) then
      R1 <= '0';
      R2 <= '0';
      R3 <= '0';
      R4 <= '1';
      G1 <= '0';
      G2 <= '0';
      G3 <= '0';
      G4 <= '0';
      B1 <= '1';
      B2 <= '1';
      B3 <= '1';
      B4 <= '1';
    end if; 
         
    if (counterX>=(80*7+Hoffset)) and (counterX<(80*8+Hoffset)) then
       R1 <= '0';
       R2 <= '0';
       R3 <= '0';
       R4 <= '0';
       G1 <= '0';
       G2 <= '0';
       G3 <= '0';
       G4 <= '1';
       B1 <= '1';
       B2 <= '1';
       B3 <= '1';
       B4 <= '1';
     end if;      
     
  end process;                                   
          
end Behavioral;
