Timing Analyzer report for tutor3
Mon Aug 30 19:44:34 2004
Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Settings
  3. Timing Analyzer Summary
  4. Clock Settings Summary
  5. Clock Setup: 'Clock_25Mhz'
  6. tsu
  7. tco
  8. th
  9. Minimum tco
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-----------------------------------------------------------------------------------------
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EPF10K70RC240-4    ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                          ;
+---------------------------------------------------------------------------------------------------------------------------------------------------
; Type                       ; Slack ; Required Time ; Actual Time                      ; From                       ; To                          ;
+----------------------------+-------+---------------+----------------------------------+----------------------------+-----------------------------+
; Worst-case tsu             ; N/A   ; None          ; 8.500 ns                         ; PB1                        ; debounce:37|SHIFT_PB[3]     ;
; Worst-case tco             ; N/A   ; None          ; 36.200 ns                        ; 8count:21|f8count:sub|2    ; MSD_SEG_B                   ;
; Worst-case th              ; N/A   ; None          ; -2.800 ns                        ; PB1                        ; debounce:37|SHIFT_PB[3]     ;
; Worst-case minimum tco     ; N/A   ; None          ; 34.300 ns                        ; 8count:21|f8count:sub|5    ; LSD_SEG_C                   ;
; Clock Setup: 'Clock_25Mhz' ; N/A   ; None          ; 42.55 MHz ( period = 23.500 ns ) ; clk_div:38|clock_100hz_int ; clk_div:38|clock_100Hz~reg0 ;
+----------------------------+-------+---------------+----------------------------------+----------------------------+-----------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock_25Mhz     ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clock_25Mhz'                                                                                                                                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period)                           ; From                                                                        ; To                                                                          ; From Clock  ; To Clock    ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------+-------------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 42.55 MHz ( period = 23.500 ns )               ; clk_div:38|clock_100hz_int                                                  ; clk_div:38|clock_100Hz~reg0                                                 ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 103.09 MHz ( period = 9.700 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 103.09 MHz ( period = 9.700 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 103.09 MHz ( period = 9.700 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 103.09 MHz ( period = 9.700 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 103.09 MHz ( period = 9.700 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 106.38 MHz ( period = 9.400 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 106.38 MHz ( period = 9.400 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 106.38 MHz ( period = 9.400 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 106.38 MHz ( period = 9.400 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 106.38 MHz ( period = 9.400 ns )               ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 112.36 MHz ( period = 8.900 ns )               ; clk_div:38|count_100hz[1]                                                   ; clk_div:38|clock_100hz_int                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 112.36 MHz ( period = 8.900 ns )               ; clk_div:38|count_100hz[0]                                                   ; clk_div:38|clock_100hz_int                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 112.36 MHz ( period = 8.900 ns )               ; clk_div:38|count_1Khz[1]                                                    ; clk_div:38|clock_1Khz_int                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 112.36 MHz ( period = 8.900 ns )               ; clk_div:38|count_1Khz[0]                                                    ; clk_div:38|clock_1Khz_int                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 112.36 MHz ( period = 8.900 ns )               ; clk_div:38|count_10Khz[1]                                                   ; clk_div:38|clock_10Khz_int                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 112.36 MHz ( period = 8.900 ns )               ; clk_div:38|count_10Khz[0]                                                   ; clk_div:38|clock_10Khz_int                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 112.36 MHz ( period = 8.900 ns )               ; clk_div:38|count_100Khz[1]                                                  ; clk_div:38|clock_100Khz_int                                                 ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 112.36 MHz ( period = 8.900 ns )               ; clk_div:38|count_100Khz[0]                                                  ; clk_div:38|clock_100Khz_int                                                 ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 116.28 MHz ( period = 8.600 ns )               ; clk_div:38|count_100hz[2]                                                   ; clk_div:38|clock_100hz_int                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 116.28 MHz ( period = 8.600 ns )               ; clk_div:38|count_1Khz[2]                                                    ; clk_div:38|clock_1Khz_int                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 116.28 MHz ( period = 8.600 ns )               ; clk_div:38|count_10Khz[2]                                                   ; clk_div:38|clock_10Khz_int                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 116.28 MHz ( period = 8.600 ns )               ; clk_div:38|count_100Khz[2]                                                  ; clk_div:38|clock_100Khz_int                                                 ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; 121.95 MHz ( period = 8.200 ns )               ; 8count:21|f8count:sub|8                                                     ; 8count:21|f8count:sub|1                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|8                                                     ; 8count:21|f8count:sub|2                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|8                                                     ; 8count:21|f8count:sub|3                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|7                                                     ; 8count:21|f8count:sub|1                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|8                                                     ; 8count:21|f8count:sub|4                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|6                                                     ; 8count:21|f8count:sub|1                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|7                                                     ; 8count:21|f8count:sub|2                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|8                                                     ; 8count:21|f8count:sub|5                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|5                                                     ; 8count:21|f8count:sub|1                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|6                                                     ; 8count:21|f8count:sub|2                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|7                                                     ; 8count:21|f8count:sub|3                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|8                                                     ; 8count:21|f8count:sub|6                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|4                                                     ; 8count:21|f8count:sub|1                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|5                                                     ; 8count:21|f8count:sub|2                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|6                                                     ; 8count:21|f8count:sub|3                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|7                                                     ; 8count:21|f8count:sub|4                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100Khz[1]                                                  ; clk_div:38|count_100Khz[2]                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100Khz[2]                                                  ; clk_div:38|count_100Khz[2]                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100Khz[0]                                                  ; clk_div:38|count_100Khz[0]                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100Khz[2]                                                  ; clk_div:38|count_100Khz[0]                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100Khz[1]                                                  ; clk_div:38|count_100Khz[1]                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_10Khz[1]                                                   ; clk_div:38|count_10Khz[2]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_10Khz[2]                                                   ; clk_div:38|count_10Khz[2]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_10Khz[0]                                                   ; clk_div:38|count_10Khz[0]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_10Khz[2]                                                   ; clk_div:38|count_10Khz[0]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_10Khz[1]                                                   ; clk_div:38|count_10Khz[1]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_1Khz[1]                                                    ; clk_div:38|count_1Khz[2]                                                    ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_1Khz[2]                                                    ; clk_div:38|count_1Khz[2]                                                    ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_1Khz[0]                                                    ; clk_div:38|count_1Khz[0]                                                    ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_1Khz[2]                                                    ; clk_div:38|count_1Khz[0]                                                    ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_1Khz[1]                                                    ; clk_div:38|count_1Khz[1]                                                    ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100hz[1]                                                   ; clk_div:38|count_100hz[2]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100hz[2]                                                   ; clk_div:38|count_100hz[2]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100hz[0]                                                   ; clk_div:38|count_100hz[0]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100hz[2]                                                   ; clk_div:38|count_100hz[0]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100hz[1]                                                   ; clk_div:38|count_100hz[1]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk_div:38|clock_1Mhz_int                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk_div:38|clock_1Mhz_int                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|8                                                     ; 8count:21|f8count:sub|8                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; debounce:37|SHIFT_PB[0]                                                     ; debounce:37|pb_debounced~reg0                                               ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; debounce:37|SHIFT_PB[1]                                                     ; debounce:37|pb_debounced~reg0                                               ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; debounce:37|SHIFT_PB[2]                                                     ; debounce:37|pb_debounced~reg0                                               ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|8                                                     ; 8count:21|f8count:sub|7                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|3                                                     ; 8count:21|f8count:sub|1                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|4                                                     ; 8count:21|f8count:sub|2                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|5                                                     ; 8count:21|f8count:sub|3                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|6                                                     ; 8count:21|f8count:sub|4                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|7                                                     ; 8count:21|f8count:sub|5                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100Khz[0]                                                  ; clk_div:38|count_100Khz[2]                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100Khz[1]                                                  ; clk_div:38|count_100Khz[0]                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100Khz[0]                                                  ; clk_div:38|count_100Khz[1]                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_10Khz[0]                                                   ; clk_div:38|count_10Khz[2]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_10Khz[1]                                                   ; clk_div:38|count_10Khz[0]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_10Khz[0]                                                   ; clk_div:38|count_10Khz[1]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_1Khz[0]                                                    ; clk_div:38|count_1Khz[2]                                                    ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_1Khz[1]                                                    ; clk_div:38|count_1Khz[0]                                                    ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_1Khz[0]                                                    ; clk_div:38|count_1Khz[1]                                                    ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100hz[0]                                                   ; clk_div:38|count_100hz[2]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100hz[1]                                                   ; clk_div:38|count_100hz[0]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|count_100hz[0]                                                   ; clk_div:38|count_100hz[1]                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|clock_100hz_int                                                  ; clk_div:38|clock_100hz_int                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|clock_1Khz_int                                                   ; clk_div:38|clock_1Khz_int                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|clock_10Khz_int                                                  ; clk_div:38|clock_10Khz_int                                                  ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|clock_100Khz_int                                                 ; clk_div:38|clock_100Khz_int                                                 ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clk_div:38|clock_1Mhz_int                                                   ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|1                                                     ; 8count:21|f8count:sub|1                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; debounce:37|SHIFT_PB[3]                                                     ; debounce:37|SHIFT_PB[2]                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; debounce:37|SHIFT_PB[2]                                                     ; debounce:37|SHIFT_PB[1]                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; debounce:37|SHIFT_PB[1]                                                     ; debounce:37|SHIFT_PB[0]                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; debounce:37|SHIFT_PB[3]                                                     ; debounce:37|pb_debounced~reg0                                               ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|2                                                     ; 8count:21|f8count:sub|1                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|3                                                     ; 8count:21|f8count:sub|2                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|2                                                     ; 8count:21|f8count:sub|2                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|4                                                     ; 8count:21|f8count:sub|3                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|3                                                     ; 8count:21|f8count:sub|3                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|5                                                     ; 8count:21|f8count:sub|4                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|4                                                     ; 8count:21|f8count:sub|4                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|6                                                     ; 8count:21|f8count:sub|5                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|5                                                     ; 8count:21|f8count:sub|5                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|7                                                     ; 8count:21|f8count:sub|6                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|6                                                     ; 8count:21|f8count:sub|6                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; 8count:21|f8count:sub|7                                                     ; 8count:21|f8count:sub|7                                                     ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; Clock_25Mhz ; Clock_25Mhz ; None                        ; None                      ; None                    ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------+-------------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------+
; tsu                                                                              ;
+-----------------------------------------------------------------------------------
; Slack ; Required tsu ; Actual tsu ; From ; To                      ; To Clock    ;
+-------+--------------+------------+------+-------------------------+-------------+
; N/A   ; None         ; 8.500 ns   ; PB1  ; debounce:37|SHIFT_PB[3] ; Clock_25Mhz ;
+-------+--------------+------------+------+-------------------------+-------------+


+---------------------------------------------------------------------------------------+
; tco                                                                                   ;
+----------------------------------------------------------------------------------------
; Slack ; Required tco ; Actual tco ; From                    ; To        ; From Clock  ;
+-------+--------------+------------+-------------------------+-----------+-------------+
; N/A   ; None         ; 36.200 ns  ; 8count:21|f8count:sub|4 ; MSD_SEG_B ; Clock_25Mhz ;
; N/A   ; None         ; 36.200 ns  ; 8count:21|f8count:sub|3 ; MSD_SEG_B ; Clock_25Mhz ;
; N/A   ; None         ; 36.200 ns  ; 8count:21|f8count:sub|2 ; MSD_SEG_B ; Clock_25Mhz ;
; N/A   ; None         ; 36.100 ns  ; 8count:21|f8count:sub|8 ; LSD_SEG_B ; Clock_25Mhz ;
; N/A   ; None         ; 36.100 ns  ; 8count:21|f8count:sub|7 ; LSD_SEG_B ; Clock_25Mhz ;
; N/A   ; None         ; 36.100 ns  ; 8count:21|f8count:sub|6 ; LSD_SEG_B ; Clock_25Mhz ;
; N/A   ; None         ; 36.100 ns  ; 8count:21|f8count:sub|8 ; LSD_SEG_A ; Clock_25Mhz ;
; N/A   ; None         ; 36.100 ns  ; 8count:21|f8count:sub|7 ; LSD_SEG_A ; Clock_25Mhz ;
; N/A   ; None         ; 36.100 ns  ; 8count:21|f8count:sub|6 ; LSD_SEG_A ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|4 ; MSD_SEG_F ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|3 ; MSD_SEG_F ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|2 ; MSD_SEG_F ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|4 ; MSD_SEG_E ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|3 ; MSD_SEG_E ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|2 ; MSD_SEG_E ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|4 ; MSD_SEG_D ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|3 ; MSD_SEG_D ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|2 ; MSD_SEG_D ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|4 ; MSD_SEG_C ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|3 ; MSD_SEG_C ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|2 ; MSD_SEG_C ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|1 ; MSD_SEG_B ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|4 ; MSD_SEG_A ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|3 ; MSD_SEG_A ; Clock_25Mhz ;
; N/A   ; None         ; 35.900 ns  ; 8count:21|f8count:sub|2 ; MSD_SEG_A ; Clock_25Mhz ;
; N/A   ; None         ; 35.800 ns  ; 8count:21|f8count:sub|4 ; MSD_SEG_G ; Clock_25Mhz ;
; N/A   ; None         ; 35.800 ns  ; 8count:21|f8count:sub|3 ; MSD_SEG_G ; Clock_25Mhz ;
; N/A   ; None         ; 35.800 ns  ; 8count:21|f8count:sub|2 ; MSD_SEG_G ; Clock_25Mhz ;
; N/A   ; None         ; 35.800 ns  ; 8count:21|f8count:sub|5 ; LSD_SEG_B ; Clock_25Mhz ;
; N/A   ; None         ; 35.800 ns  ; 8count:21|f8count:sub|5 ; LSD_SEG_A ; Clock_25Mhz ;
; N/A   ; None         ; 35.600 ns  ; 8count:21|f8count:sub|1 ; MSD_SEG_F ; Clock_25Mhz ;
; N/A   ; None         ; 35.600 ns  ; 8count:21|f8count:sub|1 ; MSD_SEG_E ; Clock_25Mhz ;
; N/A   ; None         ; 35.600 ns  ; 8count:21|f8count:sub|1 ; MSD_SEG_D ; Clock_25Mhz ;
; N/A   ; None         ; 35.600 ns  ; 8count:21|f8count:sub|1 ; MSD_SEG_C ; Clock_25Mhz ;
; N/A   ; None         ; 35.600 ns  ; 8count:21|f8count:sub|1 ; MSD_SEG_A ; Clock_25Mhz ;
; N/A   ; None         ; 35.500 ns  ; 8count:21|f8count:sub|1 ; MSD_SEG_G ; Clock_25Mhz ;
; N/A   ; None         ; 34.700 ns  ; 8count:21|f8count:sub|8 ; LSD_SEG_G ; Clock_25Mhz ;
; N/A   ; None         ; 34.700 ns  ; 8count:21|f8count:sub|7 ; LSD_SEG_G ; Clock_25Mhz ;
; N/A   ; None         ; 34.700 ns  ; 8count:21|f8count:sub|6 ; LSD_SEG_G ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|8 ; LSD_SEG_F ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|7 ; LSD_SEG_F ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|6 ; LSD_SEG_F ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|8 ; LSD_SEG_E ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|7 ; LSD_SEG_E ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|6 ; LSD_SEG_E ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|8 ; LSD_SEG_D ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|7 ; LSD_SEG_D ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|6 ; LSD_SEG_D ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|8 ; LSD_SEG_C ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|7 ; LSD_SEG_C ; Clock_25Mhz ;
; N/A   ; None         ; 34.600 ns  ; 8count:21|f8count:sub|6 ; LSD_SEG_C ; Clock_25Mhz ;
; N/A   ; None         ; 34.400 ns  ; 8count:21|f8count:sub|5 ; LSD_SEG_G ; Clock_25Mhz ;
; N/A   ; None         ; 34.300 ns  ; 8count:21|f8count:sub|5 ; LSD_SEG_F ; Clock_25Mhz ;
; N/A   ; None         ; 34.300 ns  ; 8count:21|f8count:sub|5 ; LSD_SEG_E ; Clock_25Mhz ;
; N/A   ; None         ; 34.300 ns  ; 8count:21|f8count:sub|5 ; LSD_SEG_D ; Clock_25Mhz ;
; N/A   ; None         ; 34.300 ns  ; 8count:21|f8count:sub|5 ; LSD_SEG_C ; Clock_25Mhz ;
+-------+--------------+------------+-------------------------+-----------+-------------+


+----------------------------------------------------------------------------------------+
; th                                                                                     ;
+-----------------------------------------------------------------------------------------
; Minimum Slack ; Required th ; Actual th ; From ; To                      ; To Clock    ;
+---------------+-------------+-----------+------+-------------------------+-------------+
; N/A           ; None        ; -2.800 ns ; PB1  ; debounce:37|SHIFT_PB[3] ; Clock_25Mhz ;
+---------------+-------------+-----------+------+-------------------------+-------------+


+-------------------------------------------------------------------------------------------------------+
; Minimum tco                                                                                           ;
+--------------------------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From                    ; To        ; From Clock  ;
+---------------+------------------+----------------+-------------------------+-----------+-------------+
; N/A           ; None             ; 34.300 ns      ; 8count:21|f8count:sub|5 ; LSD_SEG_C ; Clock_25Mhz ;
; N/A           ; None             ; 34.300 ns      ; 8count:21|f8count:sub|5 ; LSD_SEG_D ; Clock_25Mhz ;
; N/A           ; None             ; 34.300 ns      ; 8count:21|f8count:sub|5 ; LSD_SEG_E ; Clock_25Mhz ;
; N/A           ; None             ; 34.300 ns      ; 8count:21|f8count:sub|5 ; LSD_SEG_F ; Clock_25Mhz ;
; N/A           ; None             ; 34.400 ns      ; 8count:21|f8count:sub|5 ; LSD_SEG_G ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|6 ; LSD_SEG_C ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|7 ; LSD_SEG_C ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|8 ; LSD_SEG_C ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|6 ; LSD_SEG_D ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|7 ; LSD_SEG_D ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|8 ; LSD_SEG_D ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|6 ; LSD_SEG_E ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|7 ; LSD_SEG_E ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|8 ; LSD_SEG_E ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|6 ; LSD_SEG_F ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|7 ; LSD_SEG_F ; Clock_25Mhz ;
; N/A           ; None             ; 34.600 ns      ; 8count:21|f8count:sub|8 ; LSD_SEG_F ; Clock_25Mhz ;
; N/A           ; None             ; 34.700 ns      ; 8count:21|f8count:sub|6 ; LSD_SEG_G ; Clock_25Mhz ;
; N/A           ; None             ; 34.700 ns      ; 8count:21|f8count:sub|7 ; LSD_SEG_G ; Clock_25Mhz ;
; N/A           ; None             ; 34.700 ns      ; 8count:21|f8count:sub|8 ; LSD_SEG_G ; Clock_25Mhz ;
; N/A           ; None             ; 35.500 ns      ; 8count:21|f8count:sub|1 ; MSD_SEG_G ; Clock_25Mhz ;
; N/A           ; None             ; 35.600 ns      ; 8count:21|f8count:sub|1 ; MSD_SEG_A ; Clock_25Mhz ;
; N/A           ; None             ; 35.600 ns      ; 8count:21|f8count:sub|1 ; MSD_SEG_C ; Clock_25Mhz ;
; N/A           ; None             ; 35.600 ns      ; 8count:21|f8count:sub|1 ; MSD_SEG_D ; Clock_25Mhz ;
; N/A           ; None             ; 35.600 ns      ; 8count:21|f8count:sub|1 ; MSD_SEG_E ; Clock_25Mhz ;
; N/A           ; None             ; 35.600 ns      ; 8count:21|f8count:sub|1 ; MSD_SEG_F ; Clock_25Mhz ;
; N/A           ; None             ; 35.800 ns      ; 8count:21|f8count:sub|5 ; LSD_SEG_A ; Clock_25Mhz ;
; N/A           ; None             ; 35.800 ns      ; 8count:21|f8count:sub|5 ; LSD_SEG_B ; Clock_25Mhz ;
; N/A           ; None             ; 35.800 ns      ; 8count:21|f8count:sub|2 ; MSD_SEG_G ; Clock_25Mhz ;
; N/A           ; None             ; 35.800 ns      ; 8count:21|f8count:sub|3 ; MSD_SEG_G ; Clock_25Mhz ;
; N/A           ; None             ; 35.800 ns      ; 8count:21|f8count:sub|4 ; MSD_SEG_G ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|2 ; MSD_SEG_A ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|3 ; MSD_SEG_A ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|4 ; MSD_SEG_A ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|1 ; MSD_SEG_B ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|2 ; MSD_SEG_C ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|3 ; MSD_SEG_C ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|4 ; MSD_SEG_C ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|2 ; MSD_SEG_D ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|3 ; MSD_SEG_D ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|4 ; MSD_SEG_D ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|2 ; MSD_SEG_E ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|3 ; MSD_SEG_E ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|4 ; MSD_SEG_E ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|2 ; MSD_SEG_F ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|3 ; MSD_SEG_F ; Clock_25Mhz ;
; N/A           ; None             ; 35.900 ns      ; 8count:21|f8count:sub|4 ; MSD_SEG_F ; Clock_25Mhz ;
; N/A           ; None             ; 36.100 ns      ; 8count:21|f8count:sub|6 ; LSD_SEG_A ; Clock_25Mhz ;
; N/A           ; None             ; 36.100 ns      ; 8count:21|f8count:sub|7 ; LSD_SEG_A ; Clock_25Mhz ;
; N/A           ; None             ; 36.100 ns      ; 8count:21|f8count:sub|8 ; LSD_SEG_A ; Clock_25Mhz ;
; N/A           ; None             ; 36.100 ns      ; 8count:21|f8count:sub|6 ; LSD_SEG_B ; Clock_25Mhz ;
; N/A           ; None             ; 36.100 ns      ; 8count:21|f8count:sub|7 ; LSD_SEG_B ; Clock_25Mhz ;
; N/A           ; None             ; 36.100 ns      ; 8count:21|f8count:sub|8 ; LSD_SEG_B ; Clock_25Mhz ;
; N/A           ; None             ; 36.200 ns      ; 8count:21|f8count:sub|2 ; MSD_SEG_B ; Clock_25Mhz ;
; N/A           ; None             ; 36.200 ns      ; 8count:21|f8count:sub|3 ; MSD_SEG_B ; Clock_25Mhz ;
; N/A           ; None             ; 36.200 ns      ; 8count:21|f8count:sub|4 ; MSD_SEG_B ; Clock_25Mhz ;
+---------------+------------------+----------------+-------------------------+-----------+-------------+


+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Aug 30 19:44:32 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off tutor3 -c tutor3
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node Clock_25Mhz is an undefined clock
Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock clk_div:38|clock_1Mhz_int as buffer
    Info: Detected ripple clock clk_div:38|clock_100Khz_int as buffer
    Info: Detected ripple clock clk_div:38|clock_10Khz_int as buffer
    Info: Detected ripple clock clk_div:38|clock_1Khz_int as buffer
    Info: Detected ripple clock clk_div:38|clock_100Hz~reg0 as buffer
    Info: Detected ripple clock debounce:37|pb_debounced~reg0 as buffer
Info: Clock Clock_25Mhz has Internal fmax of 42.55 MHz between source register clk_div:38|clock_100hz_int and destination register clk_div:38|clock_100Hz~reg0 (period= 23.5 ns)
    Info: + Longest register to register delay is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_D19; Fanout = 2; REG Node = 'clk_div:38|clock_100hz_int'
        Info: 2: + IC(0.500 ns) + CELL(1.700 ns) = 2.200 ns; Loc. = LC1_D19; Fanout = 5; REG Node = 'clk_div:38|clock_100Hz~reg0'
        Info: Total cell delay = 1.700 ns ( 77.27 % )
        Info: Total interconnect delay = 0.500 ns ( 22.73 % )
    Info: - Smallest clock skew is -17.300 ns
        Info: + Shortest clock path from clock Clock_25Mhz to destination register is 7.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = Pin_91; Fanout = 8; CLK Node = 'Clock_25Mhz'
            Info: 2: + IC(4.100 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_D19; Fanout = 5; REG Node = 'clk_div:38|clock_100Hz~reg0'
            Info: Total cell delay = 2.900 ns ( 41.43 % )
            Info: Total interconnect delay = 4.100 ns ( 58.57 % )
        Info: - Longest clock path from clock Clock_25Mhz to source register is 24.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = Pin_91; Fanout = 8; CLK Node = 'Clock_25Mhz'
            Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_D9; Fanout = 4; REG Node = 'clk_div:38|clock_1Mhz_int'
            Info: 3: + IC(3.100 ns) + CELL(1.400 ns) = 12.900 ns; Loc. = LC1_D22; Fanout = 5; REG Node = 'clk_div:38|clock_100Khz_int'
            Info: 4: + IC(2.800 ns) + CELL(1.400 ns) = 17.100 ns; Loc. = LC1_D16; Fanout = 5; REG Node = 'clk_div:38|clock_10Khz_int'
            Info: 5: + IC(3.000 ns) + CELL(1.400 ns) = 21.500 ns; Loc. = LC1_D25; Fanout = 5; REG Node = 'clk_div:38|clock_1Khz_int'
            Info: 6: + IC(2.800 ns) + CELL(0.000 ns) = 24.300 ns; Loc. = LC2_D19; Fanout = 2; REG Node = 'clk_div:38|clock_100hz_int'
            Info: Total cell delay = 8.500 ns ( 34.98 % )
            Info: Total interconnect delay = 15.800 ns ( 65.02 % )
    Info: + Micro clock to output delay of source is 1.400 ns
    Info: + Micro setup delay of destination is 2.600 ns
Info: tsu for register debounce:37|SHIFT_PB[3] (data pin = PB1, clock pin = Clock_25Mhz) is 8.500 ns
    Info: + Longest pin to register delay is 17.300 ns
        Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = Pin_28; Fanout = 1; PIN Node = 'PB1'
        Info: 2: + IC(5.300 ns) + CELL(1.700 ns) = 17.300 ns; Loc. = LC5_D4; Fanout = 2; REG Node = 'debounce:37|SHIFT_PB[3]'
        Info: Total cell delay = 12.000 ns ( 69.36 % )
        Info: Total interconnect delay = 5.300 ns ( 30.64 % )
    Info: + Micro setup delay of destination is 2.600 ns
    Info: - Shortest clock path from clock Clock_25Mhz to destination register is 11.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = Pin_91; Fanout = 8; CLK Node = 'Clock_25Mhz'
        Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_D19; Fanout = 5; REG Node = 'clk_div:38|clock_100Hz~reg0'
        Info: 3: + IC(3.000 ns) + CELL(0.000 ns) = 11.400 ns; Loc. = LC5_D4; Fanout = 2; REG Node = 'debounce:37|SHIFT_PB[3]'
        Info: Total cell delay = 4.300 ns ( 37.72 % )
        Info: Total interconnect delay = 7.100 ns ( 62.28 % )
Info: tco from clock Clock_25Mhz to destination pin MSD_SEG_B through register 8count:21|f8count:sub|4 is 36.200 ns
    Info: + Longest clock path from clock Clock_25Mhz to source register is 19.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = Pin_91; Fanout = 8; CLK Node = 'Clock_25Mhz'
        Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_D19; Fanout = 5; REG Node = 'clk_div:38|clock_100Hz~reg0'
        Info: 3: + IC(3.000 ns) + CELL(1.400 ns) = 12.800 ns; Loc. = LC1_D4; Fanout = 14; REG Node = 'debounce:37|pb_debounced~reg0'
        Info: 4: + IC(6.800 ns) + CELL(0.000 ns) = 19.600 ns; Loc. = LC5_C28; Fanout = 10; REG Node = '8count:21|f8count:sub|4'
        Info: Total cell delay = 5.700 ns ( 29.08 % )
        Info: Total interconnect delay = 13.900 ns ( 70.92 % )
    Info: + Micro clock to output delay of source is 1.400 ns
    Info: + Longest register to pin delay is 15.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C28; Fanout = 10; REG Node = '8count:21|f8count:sub|4'
        Info: 2: + IC(5.100 ns) + CELL(2.700 ns) = 7.800 ns; Loc. = LC3_A52; Fanout = 1; COMB Node = 'dec_7seg:33|segment_data[5]~2'
        Info: 3: + IC(2.400 ns) + CELL(5.000 ns) = 15.200 ns; Loc. = Pin_7; Fanout = 0; PIN Node = 'MSD_SEG_B'
        Info: Total cell delay = 7.700 ns ( 50.66 % )
        Info: Total interconnect delay = 7.500 ns ( 49.34 % )
Info: th for register debounce:37|SHIFT_PB[3] (data pin = PB1, clock pin = Clock_25Mhz) is -2.800 ns
    Info: + Longest clock path from clock Clock_25Mhz to destination register is 11.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = Pin_91; Fanout = 8; CLK Node = 'Clock_25Mhz'
        Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_D19; Fanout = 5; REG Node = 'clk_div:38|clock_100Hz~reg0'
        Info: 3: + IC(3.000 ns) + CELL(0.000 ns) = 11.400 ns; Loc. = LC5_D4; Fanout = 2; REG Node = 'debounce:37|SHIFT_PB[3]'
        Info: Total cell delay = 4.300 ns ( 37.72 % )
        Info: Total interconnect delay = 7.100 ns ( 62.28 % )
    Info: + Micro hold delay of destination is 3.100 ns
    Info: - Shortest pin to register delay is 17.300 ns
        Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = Pin_28; Fanout = 1; PIN Node = 'PB1'
        Info: 2: + IC(5.300 ns) + CELL(1.700 ns) = 17.300 ns; Loc. = LC5_D4; Fanout = 2; REG Node = 'debounce:37|SHIFT_PB[3]'
        Info: Total cell delay = 12.000 ns ( 69.36 % )
        Info: Total interconnect delay = 5.300 ns ( 30.64 % )
Info: Minimum tco from clock Clock_25Mhz to destination pin LSD_SEG_C through register 8count:21|f8count:sub|5 is 34.300 ns
    Info: + Shortest clock path from clock Clock_25Mhz to source register is 19.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = Pin_91; Fanout = 8; CLK Node = 'Clock_25Mhz'
        Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_D19; Fanout = 5; REG Node = 'clk_div:38|clock_100Hz~reg0'
        Info: 3: + IC(3.000 ns) + CELL(1.400 ns) = 12.800 ns; Loc. = LC1_D4; Fanout = 14; REG Node = 'debounce:37|pb_debounced~reg0'
        Info: 4: + IC(6.800 ns) + CELL(0.000 ns) = 19.600 ns; Loc. = LC4_C28; Fanout = 10; REG Node = '8count:21|f8count:sub|5'
        Info: Total cell delay = 5.700 ns ( 29.08 % )
        Info: Total interconnect delay = 13.900 ns ( 70.92 % )
    Info: + Micro clock to output delay of source is 1.400 ns
    Info: + Shortest register to pin delay is 13.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C28; Fanout = 10; REG Node = '8count:21|f8count:sub|5'
        Info: 2: + IC(3.400 ns) + CELL(2.400 ns) = 5.800 ns; Loc. = LC1_C44; Fanout = 1; COMB Node = 'dec_7seg:36|segment_data[4]~4'
        Info: 3: + IC(2.500 ns) + CELL(5.000 ns) = 13.300 ns; Loc. = Pin_19; Fanout = 0; PIN Node = 'LSD_SEG_C'
        Info: Total cell delay = 7.400 ns ( 55.64 % )
        Info: Total interconnect delay = 5.900 ns ( 44.36 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Aug 30 19:44:34 2004
    Info: Elapsed time: 00:00:01


