Analysis & Synthesis report for tutor3
Mon Aug 30 19:44:01 2004
Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Hierarchy
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis Equations
  8. Analysis & Synthesis Files Read
  9. Analysis & Synthesis Resource Usage Summary
 10. WYSIWYG Cells
 11. General Register Statistics
 12. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------------+
; Analysis & Synthesis Summary                                        ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Aug 30 19:44:01 2004 ;
; Revision Name               ; tutor3                                ;
; Top-level Entity Name       ; tutor3                                ;
; Family                      ; FLEX10K                               ;
; Total logic elements        ; 55                                    ;
; Total pins                  ; 19                                    ;
; Total memory bits           ; 0                                     ;
+-----------------------------+---------------------------------------+


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                       ;
+--------------------------------------------------------------------------------------
; Option                                               ; Setting      ; Default Value ;
+------------------------------------------------------+--------------+---------------+
; Top-level entity name                                ; tutor3       ;               ;
; Family name                                          ; FLEX10K      ; Stratix       ;
; Auto Resource Sharing                                ; Off          ; Off           ;
; Auto RAM Replacement                                 ; On           ; On            ;
; Auto ROM Replacement                                 ; On           ; On            ;
; Remove Duplicate Logic                               ; On           ; On            ;
; Auto Open-Drain Pins                                 ; On           ; On            ;
; Auto Carry Chains                                    ; On           ; On            ;
; Cascade Chain Length                                 ; 2            ; 2             ;
; Carry Chain Length -- FLEX 10K                       ; 32           ; 32            ;
; Auto Packed Registers                                ; Off          ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area         ; Area          ;
; Auto Implement in ROM                                ; Off          ; Off           ;
; Auto Global Register Control Signals                 ; On           ; On            ;
; Auto Global Output Enable                            ; On           ; On            ;
; Auto Global Clock                                    ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                       ; Off          ; Off           ;
; Ignore SOFT Buffers                                  ; On           ; On            ;
; Ignore LCELL Buffers                                 ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                            ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                ; Off          ; Off           ;
; Ignore CASCADE Buffers                               ; Off          ; Off           ;
; Ignore CARRY Buffers                                 ; Off          ; Off           ;
; Remove Duplicate Registers                           ; On           ; On            ;
; Remove Redundant Logic Cells                         ; Off          ; Off           ;
; Power-Up Don't Care                                  ; On           ; On            ;
; NOT Gate Push-Back                                   ; On           ; On            ;
; State Machine Processing                             ; Auto         ; Auto          ;
; VHDL Version                                         ; VHDL93       ; VHDL93        ;
; Verilog Version                                      ; Verilog_2001 ; Verilog_2001  ;
; Preserve fewer node names                            ; On           ; On            ;
; Disk space/compilation speed tradeoff                ; Normal       ; Normal        ;
; Create Debugging Nodes for IP Cores                  ; off          ; off           ;
+------------------------------------------------------+--------------+---------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name               ; Setting                    ;
+--------------------+----------------------------+
; CARRY_CHAIN        ; MANUAL                     ;
; CASCADE_CHAIN      ; MANUAL                     ;
; OPTIMIZE_FOR_SPEED ; 1                          ;
; STYLE              ; FAST                       ;
+--------------------+----------------------------+


+------------+
; Hierarchy  ;
+------------+
tutor3
 |-- 8count:21
      |-- f8count:sub
 |-- dec_7seg:33
 |-- dec_7seg:36
 |-- debounce:37
 |-- clk_div:38
      |-- lpm_counter:count_1Mhz_rtl_0
           |-- alt_counter_f10ke:wysi_counter


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                               ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node                ; Logic Cells ; Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                            ;
+-------------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
; |tutor3                                   ; 55 (0)      ; 36        ; 0           ; 19   ; 19 (0)       ; 9 (0)             ; 27 (0)           ; 13 (0)          ; |tutor3                                                                        ;
;    |8count:21|                            ; 8 (0)       ; 8         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; |tutor3|8count:21                                                              ;
;       |f8count:sub|                       ; 8 (8)       ; 8         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |tutor3|8count:21|f8count:sub                                                  ;
;    |clk_div:38|                           ; 28 (23)     ; 23        ; 0           ; 0    ; 5 (5)        ; 5 (5)             ; 18 (13)          ; 5 (0)           ; |tutor3|clk_div:38                                                             ;
;       |lpm_counter:count_1Mhz_rtl_0|      ; 5 (0)       ; 5         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 5 (0)            ; 5 (0)           ; |tutor3|clk_div:38|lpm_counter:count_1Mhz_rtl_0                                ;
;          |alt_counter_f10ke:wysi_counter| ; 5 (5)       ; 5         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 5 (5)           ; |tutor3|clk_div:38|lpm_counter:count_1Mhz_rtl_0|alt_counter_f10ke:wysi_counter ;
;    |debounce:37|                          ; 5 (5)       ; 5         ; 0           ; 0    ; 0 (0)        ; 4 (4)             ; 1 (1)            ; 0 (0)           ; |tutor3|debounce:37                                                            ;
;    |dec_7seg:33|                          ; 7 (7)       ; 0         ; 0           ; 0    ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |tutor3|dec_7seg:33                                                            ;
;    |dec_7seg:36|                          ; 7 (7)       ; 0         ; 0           ; 0    ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |tutor3|dec_7seg:36                                                            ;
+-------------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+


+---------------------------------+
; Analysis & Synthesis Equations  ;
+---------------------------------+
The equations can be found in C:/qdesigns/tutorial/tutor3/tutor3.map.eqn.


+-----------------------------------------------------------------+
; Analysis & Synthesis Files Read                                 ;
+------------------------------------------------------------------
; File Name                                                ; Read ;
+----------------------------------------------------------+------+
; src/tutor3.bdf                                           ; Read ;
; c:/qdesigns/uplib/DEC_7SEG.vhd                           ; Read ;
; c:/quartus/libraries/others/maxplus2/8count.tdf          ; Read ;
; c:/quartus/libraries/others/maxplus2/f8count.bdf         ; Read ;
; c:/qdesigns/uplib/DEBOUNCE.vhd                           ; Read ;
; c:/qdesigns/uplib/CLK_DIV.vhd                            ; Read ;
; c:/quartus/libraries/megafunctions/lpm_counter.tdf       ; Read ;
; c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf ; Read ;
+----------------------------------------------------------+------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+----------------------------------------------------------
; Resource                      ; Usage                   ;
+-------------------------------+-------------------------+
; Logic cells                   ; 55                      ;
; Total combinational functions ; 46                      ;
; Total registers               ; 36                      ;
; I/O pins                      ; 19                      ;
; Maximum fan-out node          ; 8count:21|f8count:sub|8 ;
; Maximum fan-out               ; 9                       ;
; Total fan-out                 ; 198                     ;
; Average fan-out               ; 2.68                    ;
+-------------------------------+-------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 5     ;
; Number of synthesis-generated cells                    ; 50    ;
; Number of WYSIWYG LUTs                                 ; 5     ;
; Number of synthesis-generated LUTs                     ; 41    ;
; Number of WYSIWYG registers                            ; 5     ;
; Number of synthesis-generated registers                ; 31    ;
; Number of cells with combinational logic only          ; 19    ;
; Number of cells with registers only                    ; 9     ;
; Number of cells with combinational logic and registers ; 27    ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 5     ;
; Number of registers using SLOAD      ; 0     ;
; Number of registers using ACLR       ; 8     ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 4     ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Aug 30 19:43:55 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off tutor3 -c tutor3
Info: Found 1 design units and 1 entities in source file src/tutor3.bdf
    Info: Found entity 1: tutor3
Warning: Port LDN of type 8count and instance 21 is missing source signal
Warning: Port A of type 8count and instance 21 is missing source signal
Warning: Port B of type 8count and instance 21 is missing source signal
Warning: Port C of type 8count and instance 21 is missing source signal
Warning: Port D of type 8count and instance 21 is missing source signal
Warning: Port E of type 8count and instance 21 is missing source signal
Warning: Port F of type 8count and instance 21 is missing source signal
Warning: Port G of type 8count and instance 21 is missing source signal
Warning: Port H of type 8count and instance 21 is missing source signal
Warning: Port GN of type 8count and instance 21 is missing source signal
Warning: Port SETN of type 8count and instance 21 is missing source signal
Info: Using design file ../../uplib/DEC_7SEG.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: dec_7seg-rtl
    Info: Found entity 1: dec_7seg
Info: VHDL Case Statement information at DEC_7SEG.vhd(57): OTHERS choice is never selected
Info: Found 1 design units and 1 entities in source file ../../../quartus/libraries/others/maxplus2/8count.tdf
    Info: Found entity 1: 8count
Info: Found 1 design units and 1 entities in source file ../../../quartus/libraries/others/maxplus2/f8count.bdf
    Info: Found entity 1: f8count
Info: Using design file ../../uplib/DEBOUNCE.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: debounce-rtl
    Info: Found entity 1: debounce
Info: Using design file ../../uplib/CLK_DIV.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clk_div-rtl
    Info: Found entity 1: clk_div
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: CLK_DIV:38|count_1Mhz[0]~0
Info: Found 1 design units and 1 entities in source file ../../../quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file ../../../quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Warning: Output pins are stuck at VCC or GND
    Warning: Pin LSD_SEG_DP stuck at VCC
    Warning: Pin MSD_SEG_DP stuck at VCC
Info: Converted 1 single input CARRY primitives to CARRY_SUM primitives
Info: Implemented 74 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 16 output pins
    Info: Implemented 55 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
    Info: Processing ended: Mon Aug 30 19:44:01 2004
    Info: Elapsed time: 00:00:06


