subtype
voltage is real tolerance
- " tol_voltage" ;
subtype
current is real tolerance
- " tol_current" ;
nature
electrical is voltage across
current through;
terminal
t1, t2: electrical;
quantity
v across i through
t1 to t2;
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nature
electrical_vector is array(natural range
<>) of electrical;
subnature
el_vect4 is electrical_vector(0 to
3);
terminal
t3, t4: el_vect4;
quantity
vpp across ipp through
t3 to t4;
quantity
vps across ips through
t1 to t4;
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subnature
low_voltage is electrical;
tolerance
"tol_lowvoltage" across "tol_lowcurrent" through;
terminal
tx, ty: low_voltage;
quantity
vlow1 across ilow1 through
tx to ty:
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entity
simple is
port
(terminal terin, terout:electrical);
end
simple;
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