Foil 14.5 : VHDL-AMS simultaneous statements

Simultaneous statements

Simultaneous statements:

simultaneous statement allows to express the systems of differential algebraic equations (DAEs)
it is built from ordinary VHDL expressions, but the interpretation on the resultant value and the behavior differ from the evaluations relative to VHDL 1076 assignments
the analog solver determines the value of each quantity such that the values of all characteristic expressions are close to zero and thus solves the DAEs of the model
simultaneous statement assignment can take place everywhere where a signal assignment is allowed

[label:] simple_expression == simple_expression;

the expression may refer to quantities, signals, constants, shared variables, literals and functions

Resistor model:
For example a constitutive equation of a resistor may be written as:

i == v/r;

where v is an across quantity representing voltage between the two terminals and r the value of the resistance

entity resistor is

generic(r:real:=1.0E3);

port (terminal rin, rout:electrical);

end resistor;

architecture simple of resistor is

begin

quantity v across i through rin to rout;

begin

i == v/r; -- characteristic expression

end simple;

Capacitor model:

entity capacitor is

generic(r:real:=1.0E-9);

port (terminal capin, capout:electrical);

end capacitor;

architecture simple of capacitor is

begin

quantity v across i through capin to capout;

begin

i == c*v'dot; -- characteristic expression

end simple;

Tolerance group:

each expression and each characteristic quantity belongs to a tolerance group
by default, the tolerance group for a characteristic expressions with a simple simultaneous statement whose left part is the name of a quantity, is the tolerance group of this quantity
otherwise, the designer of the model has to specify the tolerance group during the declaration

i == c*v'dot tolerance "tol_lowcurrent";